ADSP-2100 Family Users Manual

The ADSP-2100 family is a collection of programmable single-chip microprocessors that share a common base architecture optimized for digital signal processing (DSP) and other high-speed numeric processing applications. The various family processors differ principally in the type of on-chip peripherals they add to the base architecture. On-chip memory, a timer, serial port(s), and parallel ports are available in different members of the family. In addition, the ADSP-21msp58/59 processors include an on-chip analog interface for voiceband signal conversion.

CONTENTS:

CHAPTER 1 INTRODUCTION

1.1 OVERVIEW ........................................................................................ 1–1

1.1.1 Functional Units ........................................................................... 1–1

1.1.2 Memory And System Interface .................................................. 1–3

1.1.3 Instruction Set .............................................................................. 1–4

1.1.4 DSP Performance ......................................................................... 1–4

1.2 CORE ARCHITECTURE .................................................................. 1–5

1.2.1 Computational Units ................................................................... 1–6

1.2.2 Address Generators & Program Sequencer ............................. 1–7

1.2.3 Buses ........................................................................................ 1–8

1.3 ON-CHIP PERIPHERALS ................................................................ 1–8

1.3.1 Serial Ports .................................................................................... 1–8

1.3.2 Timer ........................................................................................ 1–9

1.3.3 Host Interface Port ....................................................................... 1–9

1.3.4 DMA Ports .................................................................................... 1–9

1.3.5 Analog Interface ......................................................................... 1–10

1.4 ADSP-2100 FAMILY DEVELOPMENT TOOLS ......................... 1–10

1.5 ORGANIZATION OF THIS MANUAL ....................................... 1–11

CHAPTER 2 COMPUTATIONAL UNITS

2.1 OVERVIEW ........................................................................................ 2–1

2.1.1 Binary String ................................................................................. 2–1

2.1.2 Unsigned ....................................................................................... 2–1

2.1.3 Signed Numbers: Twos-Complement ...................................... 2–1

2.1.4 Fractional Representation: 1.15 .................................................. 2–2

2.1.5 ALU Arithmetic ........................................................................... 2–2

2.1.6 MAC Arithmetic .......................................................................... 2–3

2.1.7 Shifter Arithmetic ........................................................................ 2–3

2.1.8 Summary ....................................................................................... 2–4

2.2 ARITHMETIC/LOGIC UNIT (ALU) .............................................. 2–5

2.2.1 ALU Block Diagram Discussion ................................................ 2–5

2.2.2 Standard Functions ...................................................................... 2–7

2.2.3 ALU Input/Output Registers .................................................... 2–8

2.2.4 Multiprecision Capability ........................................................... 2–8

2.2.5 ALU Saturation Mode ................................................................. 2–8

2.2.6 ALU Overflow Latch Mode ....................................................... 2–9

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Contents

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2.2.7 Division ........................................................................................ 2–9

2.2.8 ALU Status .................................................................................. 2–13

2.3 MULTIPLIER/ACCUMULATOR (MAC) ................................... 2–13

2.3.1 MAC Block Diagram Discussion ............................................. 2–13

2.3.2 MAC Operations ........................................................................ 2–16

2.3.2.1 Standard Functions .............................................................. 2–16

2.3.2.2 Input Formats ....................................................................... 2–18

2.3.2.3 MAC Input/Output Registers ........................................... 2–18

2.3.2.4 MR Register Operation ....................................................... 2–18

2.3.2.5 MAC Overflow And Saturation ........................................ 2–19

2.3.2.6 Rounding Mode ................................................................... 2–20

2.3.2.7 Biased Rounding (ADSP-217x/218x/21msp5x) ............. 2–21

2.4 BARREL SHIFTER ........................................................................... 2–22

2.4.1 Shifter Block Diagram Discussion ........................................... 2–22

2.4.2 Shifter Operations ...................................................................... 2–28

2.4.2.1 Shifter Input/Output Registers ......................................... 2–28

2.4.2.2 Derive Block Exponent ....................................................... 2–29

2.4.2.3 Immediate Shifts .................................................................. 2–30

2.4.2.4 Denormalize ......................................................................... 2–31

2.4.2.5 Normalize ............................................................................. 2–33

CHAPTER 3 PROGRAM CONTROL

3.1 OVERVIEW ........................................................................................ 3–1

3.2 PROGRAM SEQUENCER ................................................................ 3–1

3.2.1 Next Address Select Logic .......................................................... 3–3

3.2.2 Program Counter & PC Stack .................................................... 3–4

3.2.3 Loop Counter & Stack ................................................................. 3–4

3.2.4 Loop Comparator & Stack .......................................................... 3–5

3.3 PROGRAM CONTROL INSTRUCTIONS ..................................... 3–8

3.3.1 JUMP Instruction ......................................................................... 3–8

3.3.1.1 Register Indirect JUMPs ........................................................ 3–8

3.3.2 CALL Instruction ......................................................................... 3–9

3.3.3 DO UNTIL Loops ........................................................................ 3–9

3.3.4 IDLE Instruction ........................................................................ 3–10

3.3.4.1 Slow IDLE ............................................................................. 3–10

3.4 INTERRUPTS ................................................................................... 3–11

3.4.1 Interrupt Servicing Sequence ................................................... 3–14

3.4.2 Configuring Interrupts .............................................................. 3–14

3.4.2.1 Interrupt Control Register (ICNTL) .................................. 3–15

3.4.2.2 Interrupt Mask Register (IMASK) ..................................... 3–16

3.4.2.3 Global Enable/Disable For Interrupts .............................. 3–17

3.4.2.4 Interrupt Force & Clear Register (IFC) ............................. 3–18

3.4.3 Interrupt Latency ....................................................................... 3–18

3.4.3.1 Timer Interrupt Latency (ADSP-2101/2105/2111/2115)3–19

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3.5 STATUS REGISTERS & STATUS STACK .................................... 3–20

3.5.1 Arithmetic Status Register (ASTAT) ....................................... 3–20

3.5.2 Stack Status Register (SSTAT) .................................................. 3–21

3.5.3 Mode Status Register (MSTAT) ............................................... 3–22

3.6 CONDITIONAL INSTRUCTIONS ............................................... 3–24

3.7 TOPPCSTACK ................................................................................. 3–25

3.7.1 TOPPCSTACK Restrictions ...................................................... 3–27

CHAPTER 4 DATA TRANSFER

4.1 OVERVIEW ........................................................................................ 4–1

4.2 DATA ADDRESS GENERATORS (DAGS) ................................... 4–1

4.2.1 DAG Registers .............................................................................. 4–1

4.2.2 Indirect Addressing ..................................................................... 4–3

4.2.2.1 Initialize L Registers To 0 For Non-Circular Addressing 4–3

4.2.3 Modulo Addressing (Circular Buffers) ..................................... 4–4

4.2.4 Calculating The Base Address ................................................... 4–5

4.2.4.1 Circular Buffer Base Address Example 1 ........................... 4–5

4.2.4.2 Circular Buffer Base Address Example 2 ........................... 4–5

4.2.4.3 Circular Buffer Operation Example 1 ................................. 4–5

4.2.4.4 Circular Buffer Operation Example 2 ................................. 4–6

4.2.5 Bit-Reverse Addressing .............................................................. 4–6

4.3 PROGRAMMNG DATA ACCESSES ............................................. 4–7

4.3.1 Variables & Arrays ...................................................................... 4–7

4.3.2 Circular Buffers ............................................................................ 4–8

4.4 PMD-DMD BUS EXCHANGE ......................................................... 4–9

4.4.1 PMD-DMD Block Diagram Discussion .................................... 4–9

CHAPTER 5 SERIAL PORTS

5.1 OVERVIEW ........................................................................................ 5–1

5.2 BASIC SPORT DESCRIPTION ........................................................ 5–1

5.2.1 Interrupts ...................................................................................... 5–4

5.2.2 SPORT Operation ........................................................................ 5–4

5.3 SPORT PROGRAMMING ................................................................ 5–4

5.3.1 SPORT Configuration ................................................................. 5–5

5.3.2 Receiving And Transmitting Data ............................................ 5–6

5.4 SPORT ENABLE ................................................................................ 5–7

5.5 SERIAL CLOCKS ............................................................................... 5–8

5.6 WORD LENGTH ............................................................................... 5–9

5.7 WORD FRAMING OPTIONS ........................................................ 5–10

5.7.1 Frame Synchronization ............................................................. 5–10

5.7.2 Frame Sync Signal Source ......................................................... 5–11

5.7.3 Normal And Alternate Framing Modes ................................. 5–13

5.7.4 Active High Or Active Low ..................................................... 5–14

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5.8 CONFIGURATION EXAMPLE ..................................................... 5–15

5.9 TIMING EXAMPLES ...................................................................... 5–16

5.10 COMPANDING AND DATA FORMAT ..................................... 5–23

5.10.1 Companding Operation Example ........................................... 5–24

5.10.2 Contention For Companding Hardware ................................ 5–25

5.10.3 Companding Internal Data ...................................................... 5–25

5.11 AUTOBUFFERING .......................................................................... 5–26

5.11.1 Autobuffering Control Register ............................................... 5–27

5.11.2 Autobuffering Example ............................................................ 5–28

5.12 MULTICHANNEL FUNCTION ................................................... 5–30

5.12.1 Multichannel Setup ................................................................... 5–30

5.12.2 Multichannel Operation ........................................................... 5–32

5.13 SPORT TIMING CONSIDERATIONS .......................................... 5–34

5.13.1 Companding Delay ................................................................... 5–34

5.13.2 Clock Synchronization Delay ................................................... 5–34

5.13.2.1 Startup Timing ..................................................................... 5–34

5.13.3 Internally Generated Frame Sync Timing .............................. 5–34

5.13.4 Transmit Interrupt Timing ....................................................... 5–36

5.13.5 Receive Interrupt Timing .......................................................... 5–36

5.13.6 Interrupt And Autobuffer Synchronization .......................... 5–38

5.13.7 Instruction Completion Latencies ........................................... 5–38

5.13.8 Interrupt And Autobuffer Service Example .......................... 5–39

5.13.9 Receive Companding Latency ................................................. 5–40

5.13.10 Interrupts With Autobuffering Enabled ................................ 5–41

5.13.11 Unusual Complications ............................................................ 5–42

CHAPTER 6 TIMER

6.1 OVERVIEW ........................................................................................ 6–1

6.2 TIMER ARCHITECTURE ................................................................. 6–1

6.3 RESOLUTION .................................................................................... 6–3

6.4 TIMER OPERATION ........................................................................ 6–3

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CHAPTER 7 HOST INTERFACE PORT

7.1 OVERVIEW ........................................................................................ 7–1

7.2 HIP PIN SUMMARY ......................................................................... 7–2

7.3 HIP FUNCTIONAL DESCRIPTION ............................................... 7–4

7.4 HIP OPERATION .............................................................................. 7–6

7.4.1 Polled Operation .......................................................................... 7–7

7.4.1.1 HIP Status Synchronization ................................................. 7–8

7.4.2 Interrupt-Driven Operation ....................................................... 7–9

7.4.3 HDR Overwrite Mode ................................................................. 7–9

7.4.4 Software Reset ............................................................................ 7–10

7.5 HIP INTERRUPTS ........................................................................... 7–10

7.6 HOST INTERFACE TIMING ......................................................... 7–11

7.7 BOOT LOADING THROUGH THE HIP ..................................... 7–16

CHAPTER 8 ANALOG INTERFACE

8.1 OVERVIEW ........................................................................................ 8–1

8.2 A/D CONVERSION ......................................................................... 8–2

8.2.1 Analog Input ................................................................................ 8–2

8.2.2 ADC ........................................................................................ 8–3

8.2.2.1 Decimation Filter ................................................................... 8–4

8.2.2.2 High Pass Filter ...................................................................... 8–5

8.3 D/A CONVERSION ......................................................................... 8–6

8.3.1 DAC ........................................................................................ 8–6

8.3.1.1 High Pass Filter ...................................................................... 8–6

8.3.1.2 Interpolation Filter ................................................................. 8–7

8.3.1.3 Analog Smoothing Filter & Programmable Gain Amp. .. 8–8

8.3.2 Differential Output Amplifier .................................................... 8–8

8.4 OPERATING THE ANALOG INTERFACE .................................. 8–9

8.4.1 Memory-Mapped Control Registers ......................................... 8–9

8.4.1.1 Analog Control Register ....................................................... 8–9

8.4.1.2 Analog Autobuffer/Powerdown Register ....................... 8–10

8.4.2 Memory-Mapped Data Registers ............................................ 8–11

8.4.3 ADC & DAC Interrupts ............................................................ 8–12

8.4.3.1 Autobuffering Disabled ...................................................... 8–12

8.4.3.2 Autobuffering Enabled ....................................................... 8–13

8.5 CIRCUIT DESIGN CONSIDERATIONS ...................................... 8–16

8.5.1 Analog Signal Input .................................................................. 8–16

8.5.2 Analog Signal Output ............................................................... 8–18

8.5.3 Voltage Reference Filter Capacitance ..................................... 8–19

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CHAPTER 9 SYSTEM INTERFACE

9.1 OVERVIEW ........................................................................................ 9–1

9.2 CLOCK SIGNALS .............................................................................. 9–3

9.2.1 Synchronization Delay ................................................................ 9–3

9.2.2 1x & 1/2x Clock Considerations ............................................... 9–4

9.3 RESET ........................................................................................ 9–4

9.4 SOFTWARE-FORCED REBOOTING ............................................. 9–4

9.4.1 ADSP-2181 Register Values For BDMA Booting .................. 9–13

9.5 EXTERNAL INTERRUPTS ............................................................. 9–14

9.5.1 Interrupt Sensitivity .................................................................. 9–14

9.6 FLAG PINS ...................................................................................... 9–15

9.7 POWERDOWN ................................................................................ 9–17

9.7.1 Powerdown Control .................................................................. 9–18

9.7.2 Entering Powerdown ................................................................ 9–19

9.7.3 Exiting Powerdown ................................................................... 9–20

9.7.3.1 Ending Powerdown With The PWD Pin .......................... 9–20

9.7.3.2 Ending Powerdown With The RESET Pin ....................... 9–21

9.7.4 Startup Time After Powerdown .............................................. 9–21

9.7.4.1 Systems Using An External TTL/CMOS Clock .............. 9–21

9.7.4.2 Systems Using A Crystal/Internal Oscillator .................. 9–22

9.7.5 Operation During Powerdown ................................................ 9–23

9.7.5.1 Interrupts & Flags ................................................................ 9–23

9.7.5.2 SPORTS ................................................................................. 9–23

9.7.5.3 HIP During Powerdown ..................................................... 9–24

9.7.5.4 IDMA Port During Powerdown (ADSP-2181) ................ 9–25

9.7.5.5 BDMA Port During Powerdown (ADSP-2181) ............... 9–26

9.7.5.6 Analog Interface (ADSP-21msp5x) ................................... 9–26

9.7.6 Conditions For Lowest Power Consumption ........................ 9–26

9.7.7 PWDACK Pin ............................................................................. 9–29

9.7.8 Using Powerdown As A Non-Maskable Interrupt ............... 9–30

CHAPTER 10 MEMORY INTERFACE

10.1 OVERVIEW ...................................................................................... 10–1

10.2 PROGRAM MEMORY INTERFACE ............................................ 10–3

10.2.1 External Program Memory Read/Write ................................ 10–3

10.2.2 Program Memory Maps ............................................................ 10–5

10.2.3 ROM Program Memory Maps ................................................. 10–6

10.3 DATA MEMORY INTERFACE ................................................... 10–10

10.3.1 External Data Memory Read/Write ..................................... 10–10

10.3.2 Data Memory Maps ................................................................. 10–11

10.3.3 Memory-Mapped Peripherals................................................ 10–14

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10.4 BOOT MEMORY INTERFACE .................................................... 10–15

10.4.1 Boot Pages ................................................................................. 10–15

10.4.2 Powerup Boot & Software Reboot ........................................ 10–16

10.4.3 Boot Memory Access ............................................................... 10–17

10.4.4 Boot Loading Sequence ........................................................... 10–17

10.5 BUS REQUEST/GRANT .............................................................. 10–21

10.6 ADSP-2181 MEMORY INTERFACES ......................................... 10–23

10.6.1 ADSP-2181 Program Memory Interface ............................... 10–25

10.6.2 ADSP-2181 Data Memory Interface ...................................... 10–30

10.6.3 ADSP-2181 Byte Memory Interface ....................................... 10–32

10.6.4 ADSP-2181 I/O Memory Space ............................................. 10–32

10.6.5 ADSP-2181 Composite Memory Select................................. 10–35

10.6.6 External Memory Read – Overlays & I/O Memory ........... 10–36

10.6.7 External Memory Write – Overlays & I/O Memory .......... 10–37

10.7 MEMORY INTERFACE SUMMARY (ALL PROCESSORS) ... 10–37

CHAPTER 11 DMA PORTS

11.1 OVERVIEW ...................................................................................... 11–1

11.2 BDMA PORT .................................................................................... 11–2

11.2.1 BDMA Port Functional Description ........................................ 11–4

11.2.2 BDMA Control Registers .......................................................... 11–4

11.2.3 Byte Memory Word Formats ................................................... 11–9

11.2.4 BDMA Booting ........................................................................... 11–9

11.2.4.1 Development Software Features for BDMA Booting . 11–11

11.3 IDMA PORT ................................................................................... 11–12

11.3.1 IDMA Port Pin Summary ....................................................... 11–12

11.3.2 IDMA Port Functional Description ....................................... 11–14

11.3.3 Modifying Control Registers for IDMA ............................... 11–16

11.3.4 IDMA Timing ........................................................................... 11–17

11.3.4.1 Address Latch Cycle .......................................................... 11–17

11.3.4.2 Long Read Cycle ................................................................ 11–18

11.3.4.3 Short Read Cycle ................................................................ 11–20

11.3.4.4 Long Write Cycle ............................................................... 11–21

11.3.4.5 Short Write Cycle ............................................................... 11–23

11.3.5 Boot Loading Through The IDMA Port ............................... 11–24

11.3.6 DMA Cycle Stealing, DMA Hold Offs, and IACK ............. 11–25

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CHAPTER 12 PROGRAMMING MODEL

12.1 OVERVIEW ...................................................................................... 12–1

12.1.1 Data Address Generators ......................................................... 12–2

12.1.1.1 Always Initialize L Registers ............................................. 12–2

12.1.2 Program Sequencer ................................................................... 12–4

12.1.2.1 Interrupts .............................................................................. 12–4

12.1.2.2 Loop Counts ......................................................................... 12–4

12.1.2.3 Status And Mode Bits .......................................................... 12–5

12.1.2.4 Stacks ..................................................................................... 12–5

12.1.3 Computational Units ................................................................. 12–6

12.1.4 Bus Exchange .............................................................................. 12–6

12.1.5 Timer ...................................................................................... 12–6

12.1.6 Serial Ports .................................................................................. 12–7

12.1.7 Memory Interface & SPORT Enables ...................................... 12–7

12.1.8 Host Interface ............................................................................. 12–8

12.1.9 Analog Interface ......................................................................... 12–8

12.2 PROGRAM EXAMPLE ................................................................... 12–8

12.2.1 Example Program: Setup Routine Discussion ..................... 12–10

12.2.2 Example Program: Interrupt Routine Discussion ............... 12–11

CHAPTER 13 HARDWARE EXAMPLES

13.1 OVERVIEW ...................................................................................... 13–1

13.2 BOOT LOADING FROM HOST USING BUS REQUEST .......... 13–2

13.3 SERIAL PORT TO CODEC INTERFACE ..................................... 13–5

13.4 SERIAL PORT TO DAC INTERFACE .......................................... 13–8

13.5 SERIAL PORT TO ADC INTERFACE ........................................ 13–10

13.6 SERIAL PORT TO SERIAL PORT INTERFACE ....................... 13–12

13.7 80C51 INTERFACE TO HOST INTERFACE PORT ................. 13–13

CHAPTER 14 SOFTWARE EXAMPLES

14.1 OVERVIEW ...................................................................................... 14–1

14.2 SYSTEM DEVELOPMENT PROCESS .......................................... 14–2

14.3 SINGLE-PRECISION FIR TRANSVERSAL FILTER .................. 14–4

14.4 CASCADED BIQUAD IIR FILTER ............................................... 14–6

14.5 SINE APPROXIMATION ............................................................... 14–7

14.6 SINGLE-PRECISION MATRIX MULTIPLY ................................ 14–9

14.7 RADIX-2 DECIMATION-IN-TIME FFT ..................................... 14–11

14.7.1 Main Module ............................................................................ 14–11

14.7.2 DIT FFT Subroutine ................................................................. 14–13

14.7.3 Bit-Reverse Subroutine ........................................................... 14–18

14.7.4 Block Floating-Point Scaling Subroutine .............................. 14–19

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CHAPTER 15 INSTRUCTION SET REFERENCE

15.1 QUICK LIST OF INSTRUCTIONS ................................................ 15–1

15.2 OVERVIEW ...................................................................................... 15–2

15.3 INSTRUCTION TYPES & NOTATION CONVENTIONS ........ 15–3

15.4 MULTIFUNCTION INSTRUCTIONS .......................................... 15–4

15.4.1 ALU/MAC With Data & Program Memory Read ............... 15–4

15.4.2 Data & Program Memory Read ............................................... 15–6

15.4.3 Computation With Memory Read .......................................... 15–6

15.4.4 Computation With Memory Write .......................................... 15–6

15.4.5 Computation With Data Register Move ................................. 15–7

15.5 ALU, MAC & SHIFTER INSTRUCTIONS ................................... 15–9

15.5.1 ALU Group ................................................................................. 15–9

15.5.2 MAC Group .............................................................................. 15–10

15.5.3 Shifter Group ............................................................................ 15–11

15.6 MOVE: READ & WRITE ............................................................... 15–12

15.7 PROGRAM FLOW CONTROL ................................................... 15–14

15.8 MISCELLANEOUS INSTRUCTIONS ........................................ 15–16

15.9 EXTRA CYCLE CONDITIONS ................................................... 15–18

15.9.1 Multiple Off-Chip Memory Accesses ................................... 15–18

15.9.2 Wait States ................................................................................ 15–18

15.9.3 SPORT Autobuffering & DMA .............................................. 15–18

15.10 INSTRUCTION SET SYNTAX ..................................................... 15–19

15.10.1 Punctuation & Multifunction Instructions ........................... 15–19

15.10.2 Syntax Notation Example ....................................................... 15–19

15.10.3 Status Register Notation ......................................................... 15–20

ALU Add/Add with Carry ................................................................... 15–23

Subtract X-Y/Subtract X-Y with Borrow .................................... 15–25

Subtract Y-X/Subtract Y-X with Borrow .................................... 15–27

AND, OR, XOR .............................................................................. 15–29

Test Bit, Clear Bit, Set Bit, Toggle Bit .......................................... 15–31

Pass/Clear ...................................................................................... 15–33

Negate ........................................................................................... 15–35

NOT ................................................................................................ 15–36

Absolute Value ............................................................................... 15–37

Increment ........................................................................................ 15–38

Decrement ....................................................................................... 15–39

Divide ............................................................................................. 15–40

Generate ALU Status ..................................................................... 15–42

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MAC Multiply ......................................................................................... 15–43

Multiply/Accumulate ................................................................... 15–45

Multiply/Subtract ......................................................................... 15–47

Clear ............................................................................................... 15–49

Transfer MR .................................................................................... 15–50

Conditional MR Saturation .......................................................... 15–51

SHIFTER

Arithmetic Shift .............................................................................. 15–52

Logical Shift .................................................................................... 15–54

Normalize ...................................................................................... 15–56

Derive Exponent ............................................................................ 15–58

Block Exponent Adjust .................................................................. 15–60

Arithmetic Shift Immediate .......................................................... 15–62

Logical Shift Immediate ................................................................ 15–64

MOVE

Register Move ................................................................................. 15–65

Load Register Immediate ............................................................. 15–67

Data Memory Read (Direct Address) ......................................... 15–69

Data Memory Read (Indirect Address) ...................................... 15–70

Program Memory Read (Indirect Address) ............................... 15–71

Data Memory Write (Direct Address) ........................................ 15–72

Data Memory Write (Indirect Address) ..................................... 15–73

Program Memory Write (Indirect Address) .............................. 15–75

I/O Space Read/Write .................................................................. 15–76

PROGRAM FLOW

JUMP ............................................................................................. 15–77

CALL ............................................................................................. 15–78

JUMP or CALL on Flag In Pin ..................................................... 15–79

Modify Flag Out Pin ...................................................................... 15–80

Return From Subroutine (RTS) .................................................... 15–81

Return From Interrupt (RTI) ........................................................ 15–82

Do Until ......................................................................................... 15–83

IDLE ......................................................................................... 15–85

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MISC

Stack Control .................................................................................. 15–86

Mode Control ................................................................................. 15–89

Modify Address Register .............................................................. 15–91

NOP .................................................................................... 15–92

Interrupt Enable/Disable ............................................................. 15–93

MULTIFUNCTION

ALU/MAC/SHIFT Operation with Memory Read .................... 15–94

ALU/MAC/SHIFT Operation with Register to Register Move . 15–98

ALU/MAC/SHIFT Operation with Memory Write ................. 15–101

Data & Program Memory Read ................................................. 15–105

ALU/MAC Operation with Data & Program Memory Read ... 15–106

APPENDIX A INSTRUCTION CODING

A.1 OPCODES ....................................................................................... A–1

A.2 ABBREVIATION CODING ............................................................. A–7

APPENDIX B DIVISION EXCEPTIONS

B.1 DIVISION FUNDAMENTALS ........................................................ B–1

B.1.1 Signed Division ............................................................................ B–1

B.1.2 Unsigned Division ....................................................................... B–2

B.1.3 Output Formats ............................................................................ B–2

B.1.4 Integer Division ........................................................................... B–3

B.2 ERROR CONDITIONS ..................................................................... B–3

B.2.1 Negative Divisor Error ................................................................ B–3

B.2.2 Unsigned Division Error ............................................................. B–4

B.3 SOFTWARE SOLUTION .................................................................. B–4

APPENDIX C NUMERIC FORMATS

C.1 OVERVIEW ....................................................................................... C–1

C.2 UNSIGNED OR SIGNED: TWOS-COMPLEMENT FORMAT .. C–1

C.3 INTEGER OR FRACTIONAL ......................................................... C–1

C.4 BINARY MULTIPLICATION ......................................................... C–3

C.4.1 Fractional Mode And Integer Mode ........................................ C–4

C.5 BLOCK FLOATING-POINT FORMAT ......................................... C–5

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APPENDIX D INTERRUPT VECTOR ADDRESSES

D.1 INTERRUPT VECTOR ADDRESSES ............................................. D–1

APPENDIX E CONTROL/STATUS REGISTERS

E.1 OVERVIEW ........................................................................................ E-1

INDEX

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