EBOOK - Analog Circuit Design - High speed Clock and Data Recovery - High performance Amplifiers - Power Management (Michiel Steyaert & Arthur H.M. van Roermund)

The first chapter of this book is on high-speed clock and data recovery circuits (CDR). In modern high speed communication systems, the recovery of the clock is becoming a key in order to recover accurate the data. Most of the architectures used are PLL based topologies, but alternative ways such as time-to-digital converters are becoming in the picture as well. The major requirement for high speed CDR is the jitter requirement since this will directly effect the bit-error-rate (BER). For that
first the basics mechanisms will be addressed, followed by PLL circuits and finally by special alternative topologies.
The first paper, of Anthony Sanders, deals with the fundamental stochastic issues in the jitter process. The different sources and definitions are discussed. Also the effect of channels and the ISI (intersymbol interference) have an effect on the jitter performances. As a result more and more there is a need for a reliable stochastic prediction of the different sources towards the jitter of CDR systems.

The second paper, of Massimo Pozzoni, addresses CDR circuits for lossy channels. Since serial communication speeds reaches the 10 Gb/s, also the channel attenuation, and as such the required channel equalization becomes important. The band limitation will result in ISI and as a result analog boost (to partially equalize the channel) and decision feedback equalizations (DFE) techniques can be used. The work presents some examples and design with possibilities to achieve 10 Gb/s serial communication systems.
The third paper, of Jan Crols, addresses the design methodology. Those complex PLL CDR circuits require very defined design flows to cope with the ever faster track from differentiating IP to commodity IP block in the CMOS serial interface communication circuits. Following the design flow, examples of 10 Gb/s links in 130 nm and PCI-Express links in 90 nm CMOS are demonstrated.
The fourth paper, of Michael Perrott, describes the design approach of high speed high performance CDR by using a good mix between analog and digital building blocks: due to the trends of more digital, a clear trade off between the different building blocks are required. It is shown that by a good selection of a combined implementation of both analog an digital circuits better performances can be achieved. This is both the case in the loop filter, phase detector and VCO. The result is 2.5 GB/s CDR circuits with jitter performances of better than 1.4 ps rms.

Part I High-Speed Clock and Data Recovery
Fundamental Stochastic Jitter Processes Associated with Clock and Data Recovery: A Tutorial....................................... 3
Anthony Fraser Sanders Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links........................................... 17
M. Pozzoni, S. Erba, P. Viola, M. Pisati, E. Depaoli, D. Sanzogni, R. Brama, D. Baldi, M. Repossi and F. Svelto
Top-Down Bottom-Up Design Methodology for Fast and Reliable Serdes evelopments in nm Technologies.................................... 35
Jan Crols Mixed-Signal Implementation Strategies for High Performance Clock
and Data Recovery Circuits ......................................... 47
Michael H. Perrott
Jointly Optimize Equalizer and CDR for Multi-Gigabit/s SerDes ........ 63
Song Wu and Robert Payne
Time to Digital Conversion: An Alternative View on Synchronization.... 77
J. Daniels, W. Dehaene and M. Steyaert
Part II High-Performance Amplifiers
Dynamic Offset Cancellation in Operational Amplifiers and Instrumentation Amplifiers.......................................... 99
Johan H. Huijsing
Current Sense Amplifiers with Extended Common Mode Voltage Range. . 125
W.J. Kindt
Low-Voltage Power-Efficient Amplifiers for Emerging Applications......147
A. L´ opez-Martin, R.G. Carvajal, E. L´ opez-Morillo, L. Acosta,
T. S´ anchez-Rodriguez, C. Rubia-Marcos and J. Ram´ırez-Angulo Integrated Amplifier Architectures for Efficient Coupling to the Nervous System............................................................167
Timothy Denison, Gregory Molnar and Reid R. Harrison Transimpedance Amplifiers for Extremely High Sensitivity Impedance Measurements on Nanodevices.......................................193
Giorgio Ferrari, Fabio Gozzini and Marco Sampietro
Design of High Power Class-D Audio Amplifiers.......................209
Marco Berkhout
Part III Power Management
Single-Inductor Multiple-Output Dc-Dc Converters....................233
Massimiliano Belloni, Edoardo Bonizzoni and Franco Maloberti
Enhanced Ripple Regulators........................................255
Richard Redl
Robust DCDC Converter for Automotive Applications..................269
Ivan Koudar
Highly Integrated Power Managemant Integrated Circuits in Advanced
Cmos Process Technologies..........................................303
Mario Manninger
Wideband Efficient Amplifiers for On-Chip Adaptive Power
Management Applications...........................................317
L´ azaro Marco, Vahid Yousefzadeh, Albert Garc´ıa-Tormo, Alberto Poveda,
Dragan Maksimovi´ c and Eduard Alarc´ on
Design Methodology and Circuit Techniques for Any-Load Stable LDOs
with Instant Load Regulation and Low Noise..........................339

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The first chapter of this book is on high-speed clock and data recovery circuits (CDR). In modern high speed communication systems, the recovery of the clock is becoming a key in order to recover accurate the data. Most of the architectures used are PLL based topologies, but alternative ways such as time-to-digital converters are becoming in the picture as well. The major requirement for high speed CDR is the jitter requirement since this will directly effect the bit-error-rate (BER). For that
first the basics mechanisms will be addressed, followed by PLL circuits and finally by special alternative topologies.
The first paper, of Anthony Sanders, deals with the fundamental stochastic issues in the jitter process. The different sources and definitions are discussed. Also the effect of channels and the ISI (intersymbol interference) have an effect on the jitter performances. As a result more and more there is a need for a reliable stochastic prediction of the different sources towards the jitter of CDR systems.

The second paper, of Massimo Pozzoni, addresses CDR circuits for lossy channels. Since serial communication speeds reaches the 10 Gb/s, also the channel attenuation, and as such the required channel equalization becomes important. The band limitation will result in ISI and as a result analog boost (to partially equalize the channel) and decision feedback equalizations (DFE) techniques can be used. The work presents some examples and design with possibilities to achieve 10 Gb/s serial communication systems.
The third paper, of Jan Crols, addresses the design methodology. Those complex PLL CDR circuits require very defined design flows to cope with the ever faster track from differentiating IP to commodity IP block in the CMOS serial interface communication circuits. Following the design flow, examples of 10 Gb/s links in 130 nm and PCI-Express links in 90 nm CMOS are demonstrated.
The fourth paper, of Michael Perrott, describes the design approach of high speed high performance CDR by using a good mix between analog and digital building blocks: due to the trends of more digital, a clear trade off between the different building blocks are required. It is shown that by a good selection of a combined implementation of both analog an digital circuits better performances can be achieved. This is both the case in the loop filter, phase detector and VCO. The result is 2.5 GB/s CDR circuits with jitter performances of better than 1.4 ps rms.

Part I High-Speed Clock and Data Recovery
Fundamental Stochastic Jitter Processes Associated with Clock and Data Recovery: A Tutorial....................................... 3
Anthony Fraser Sanders Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links........................................... 17
M. Pozzoni, S. Erba, P. Viola, M. Pisati, E. Depaoli, D. Sanzogni, R. Brama, D. Baldi, M. Repossi and F. Svelto
Top-Down Bottom-Up Design Methodology for Fast and Reliable Serdes evelopments in nm Technologies.................................... 35
Jan Crols Mixed-Signal Implementation Strategies for High Performance Clock
and Data Recovery Circuits ......................................... 47
Michael H. Perrott
Jointly Optimize Equalizer and CDR for Multi-Gigabit/s SerDes ........ 63
Song Wu and Robert Payne
Time to Digital Conversion: An Alternative View on Synchronization.... 77
J. Daniels, W. Dehaene and M. Steyaert
Part II High-Performance Amplifiers
Dynamic Offset Cancellation in Operational Amplifiers and Instrumentation Amplifiers.......................................... 99
Johan H. Huijsing
Current Sense Amplifiers with Extended Common Mode Voltage Range. . 125
W.J. Kindt
Low-Voltage Power-Efficient Amplifiers for Emerging Applications......147
A. L´ opez-Martin, R.G. Carvajal, E. L´ opez-Morillo, L. Acosta,
T. S´ anchez-Rodriguez, C. Rubia-Marcos and J. Ram´ırez-Angulo Integrated Amplifier Architectures for Efficient Coupling to the Nervous System............................................................167
Timothy Denison, Gregory Molnar and Reid R. Harrison Transimpedance Amplifiers for Extremely High Sensitivity Impedance Measurements on Nanodevices.......................................193
Giorgio Ferrari, Fabio Gozzini and Marco Sampietro
Design of High Power Class-D Audio Amplifiers.......................209
Marco Berkhout
Part III Power Management
Single-Inductor Multiple-Output Dc-Dc Converters....................233
Massimiliano Belloni, Edoardo Bonizzoni and Franco Maloberti
Enhanced Ripple Regulators........................................255
Richard Redl
Robust DCDC Converter for Automotive Applications..................269
Ivan Koudar
Highly Integrated Power Managemant Integrated Circuits in Advanced
Cmos Process Technologies..........................................303
Mario Manninger
Wideband Efficient Amplifiers for On-Chip Adaptive Power
Management Applications...........................................317
L´ azaro Marco, Vahid Yousefzadeh, Albert Garc´ıa-Tormo, Alberto Poveda,
Dragan Maksimovi´ c and Eduard Alarc´ on
Design Methodology and Circuit Techniques for Any-Load Stable LDOs
with Instant Load Regulation and Low Noise..........................339

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Chuyên mục: C. Bài giảng C. Bài giảng chuyên ngành Điện - Điện tử (Electrical & Electronic) C. Bài giảng kỹ thuật