EBOOK - Computer Organization and Design 3th Ed (D. A. Patterson & J. L. Hennessy)

EBOOK - Tổ chức và thiết kế máy tính (D. A. Patterson & J. L. Hennessy) - 679 Trang.

In addition to thoroughly updating every aspect of the text to reflect the most current computing technology, the third edition

*Uses standard 32-bit MIPS 32 as the primary teaching ISA.
*Presents the assembler-to-HLL translations in both C and Java.
*Highlights the latest developments in architecture in Real Stuff sections:

+ Intel IA-32
+ Power PC 604
+ Google's PC cluster
+ Pentium P4
+ SPEC CPU2000 benchmark suite for processors
+ SPEC Web99 benchmark for web servers
+ EEMBC benchmark for embedded systems
+ AMD Opteron memory hierarchy
+ AMD vs. 1A-64


a Computer Abstractions and Technology 2
1.1 Introducti o n 3
1.2 Below Your Program I I
1.3 Under th e Covers IS
1.4 Real Stuff: Manufa cturin g Pentium 4 Chips 28
1.5 Fallacies and Pitfalls 33
1.6 Concluding Remarks 35
1. 7 Historical Perspective and Further Reading 36
1.8 Exercises 36
Information Technology for the 4 Billion without IT 44
B Instructions: Language of the Computer 46
2. 1 Introduction 48
2.2 Operations of the Computer Hardware 49
2.3 Operands of the Computer Hardware 52
2.4 Representing Instructions in th e Computer 60
2.5 Logical Operations 68
2.6 Instructions for Makin g Decisions 72
2.7 Supporting Procedures in Computer Hardware 79
2.8 Communicating with People 90
2.9 MIPS Addressing for 32-Bit Immed iates and Addresses 95
2.10 Translating and Starting a Program 106
2. I I How Compilers Optimize 116
2. 12 How Compilers Work: An Introduction 12 1
2. 13 ACSort Exa mp le to Put It All Together 12 1
2. 14 Implementing an Object-O ri ent ed Lan gua ge 130
2.1 5 Arrays ve rsus Pointers 130
2.1 6 Real Stuff: IA-32 Instructions 134
2.1 7 Fallacies and Pitfalls 143
2.18 Concluding Remarks 145
2. 19 Historical Perspective and Further Readin g 147
2.20 Exercises 147
Helping Save Our Environment with Data 156
II Arithmetic for Computers 158
3. 1 Introduction 160
3.2 Signed and Unsigned Numbers 160
3.3 Add itio n and Subtra ction 170
3.4 Multip lica tion 176
3.5 Division 183
3.6 Floating Point 189
3.7 Rea l Stuff: Floating Po int in th e IA-32 217
3.8 Fallacies and Pitfalls 220
3.9 Concluding Remarks 225
3.10 Historical Perspective and Further Readin g 229
3. 11 Exercises 229
Reconstructing the Ancient World 236
a Assessing and Understanding Performance 238
4.1 Introduction 240
4.2 CPU Perfo nnan ce and Its Fa ctors 246
4.3 Evaluating Performan ce 254
4.4 Rea l Stuff: Two SPEC Benchmarks and th e Performance of Recent
Intel Processors 259
4.5 Fallacies and Pitfalls 266
4.6 Concluding Remarks 270
4.7 Historical Perspective and Further Readin g 272
4.8 Exercises 272
Moving People Faster and More Safely 280
The Processor: Datapath and Control 282
Introducti o n 284
Logic Design Co nven ti o ns 289
Building a Datapath 292
A Simple Implementati on Sc heme 300
A Multicycle Implementati o n 3 18
Exceptions 340
Microprogramming: Simplifying Co ntrol Design 346
An Introductio n to Digital Design Using a Hardware Design
Language 346
Real Stuff: The O rga niza ti on of Recent Pentium
Implementati ons 347
Fallac ies a nd Pitfalls 350
Co ncludin g Remarks 352
Histori cal Perspective and Further Reading 353
Exercises 354
Empowering the Disabled 366
II Enhancing Performance with Pipelining 368
6.1 An OverviewofPip elinin g 370
6.2 A Pipelined Datapath 384
6.3 Pipelined Co nt ro l 399
6.4 Data Hazards and Forwardin g 402
6.5 Data Hazards and Stall s 41 3
6.6 Branch Ha zards 416
6.7 Using a Hardware Description Language to Describe and Model a
Pipeline 426
6.8 Exceptions 427
6.9 Adva nced Pipelining: Extra cting More Performance 432
6.10 Real Stuff: The Pentium 4 Pipeline 448
6.11 Fallacies and Pitfalls 45 1
6. 12 Co ncludin g Remarks 452
6. 13 Histori cal Perspective and Further Reading 454
6.14 Exercises 454
Mass Communication without Gatekeepers 464
vIII Contents
II Large and Fast: Exploiting Memory Hierarchy 466
7.1 Introduction 468
7.2 The Basics of Caches 473
7.3 Measuring and Improving Cache Performance 492
7.4 Virtual Memory 5 11
7.5 A Common Framework for Memory Hierarc hi es 538
7.6 Real Stuff: The Pentium P4 and the AMD Opteron Memory
Hierarchies 546
7.7 Fallacies and Pitfalls 550
7.8 Concluding Remarks 552
7.9 Historical Perspective and Further Reading 555
7. 10 Exercises 555
Saving the World 's Art Treasures 562
EI Storage, Networks, and Other Peripherals 564
8.1 Introduction 566
8.2 Disk Storage and Dependability 569
8.3 Networks 580
8.4 Buses and Other Connections between Processors, Memory, and I/O
Devices 581
8.5 Interfacin g I/O Devices to the Processor, Memory, and Operating
System 588
8.6 I/O Performance Measures: Examples from Disk and File
Systems 597
8.7 Designing an I/O System 600
8.8 Real Stuff: A Digital Camera 603
8.9 Fallacies and Pitfalls 606
8.10 Concluding Remarks 609
8.11 Historical Perspective and Further Reading 6 11
8.12 Exercises 6 11
Saving Uves through Better Diagnosis 622
ra Multiprocessors and Clusters 9-2
9. 1 Introduction 9-4
9.2 Progra mmin g Multiprocessors 9-8
9.3 Multiprocessors Connected by a Single Bus 9-11
9.4 Multiprocesso rs Co nn ected by a Netwo rk 9-20
9.5 Clusters 9-25
9.6 Netwo rk Topologies 9-27
9.7 Multiprocesso rs Inside a Chip and Multithreadin g 9-30
9.8 Rea l Stuff: The Coogle Cluster of PCs 9-34
9.9 Fall ac ies a nd Pitfall s 9-39
9. 10 Co ncludin g Remarks 9-42
9. I I Histori cal Perspective and Further Readin g 9-47
9. 12 Exercises 9-55
a Assemblers, Linkers, and the SPIM Simulator A-2
A. I Int ro ducti o n A-3
A.2 Assemblers A- I0
A.3 Linkers A- 18
A A Loadin g A- 19
A.5 Memory Usage A-20
A.6 Procedure Call Co nventi o n A-22
A.7 Exceptio ns and Interrupts A-33
A.8 Input and O utput A-38
A.9 SPIM A- 40
A. IO MIPS R2000 Asse mbly Lan guage A- 45
A. I I Co ncludin g Rema rks A-8 I
A.I2 Exercises A-82
[I The Basics of Logic Design B-2
8.1 Int ro ductio n B-3
8. 2 Ga tes, Truth Tables, and Logic Equatio ns B-4
8. 3 Co mbin ati onal Logic B-8
B.4 Us ing a Hard wa re Descripti on Language B-20
8. 5 Co nstructin g a Basic Arithm eti c Logic Unit B-26
B.6 Faster Additi o n: Ca r ry Loo kahead B-38
B.7 Cloc ks B-47
B.8 Memory El ement s: Flip -fl op s, Latches, a nd Registers B-49
8.9 Memory El ement s: SRAMs and DRAMs B-57
8. 10 Finite State Machin es B-67
B. I I Timing Methodologies B-72
x Contents
B.12 Fi eld ProgrJmlT1 able Devices B-77
B.13 Co ncludin g Remarks B-78
8.14 Exercises B-79
Mapping Control to Hardware C·2
C I Int ro ducti o n C-3
C2 Implementin g Co mbin ati o nal Co nt ro l Units C-4
C3 Implementin g Finite State Machin e Co ntro l C-8
CA Implementin g th e Next-State Funct ion with a Sequencer C-2 1
C5 T rJ nslatin g a Mi cro progra m to Hard wa re C-27
C6 Co ncludin g Remarks C-3 1
C7 Exercises C-32
A Survey of RiSe Architectures for Desktop, Server,
and Embedded Computers 1).2
D. I Int ro ducti o n D-3
D.2 Addressing Modes a nd Instructio n Form ats D-5
D.3 Instructi ons: Th e MIPS Co re Subse t D-9
D.4 Instructi ons: Multim edia Extensions of th e Desktop/Server RI SCs D- 16
D.5 Instructi ons: Digital Signal-Process ing Extensio ns o f th e
Embedd ed RI SCs D- 19
D.6 Instructi ons: Co mmon Extensi o ns to MIPS Co re D-20
D.7 Instructi ons Unique to MIPS6 4 D-25
D.8 Instructi ons Unique to Alpha D-27
D.9 Instructi ons Unique to SPARC v.9 D-29
D.lO Instructi ons Unique to Powe rPC D-32
D. II Instructi ons Unique to PA- RI SC 2.0 D-34
D.12 Instructi ons Unique to ARM D-36
D.13 Instructi ons Unique to Thumb D-38
D. 14 Instructi ons Unique to SuperH D-39
D.15 Instructi ons Unique to M32 R D-40
D.16 Instructi ons Unique to MIPSI6 D- 41
D.17 Co ncludin g Remarks D-43
D.18 Ackn owledgments D-46
D.19 References D-47
Index I- I
tel Glossary G- I
II Further Reading FR- I



No comments: