EBOOK - Introduction to Embedded System Design Using Field Programmable Gate Arrays (Rahul Dubey)


EBOOK - Giới thiệu về Thiết kế hệ thống nhúng Sử dụng Mảng cổng lập trình trường (Rahul Dubey).

around the general purpose processor and microcontrollers. The use of field programmable gate array (FPGA) in icroprocessor-based embedded systems is often for glue logic or for off-loading the processor from tasks that require fast updates. The motivation for writing this text is to present a single source of information that can be used to understand how a FPGA and the Hardware Description Language (HDL) can be used in the design of embedded digital systems.

Digital design methodology has undergone several changes over the past three decades. The use of FPGA and HDL for implementing digital logic has become widespread in the last decade. The use ofFPGA in embedded systems is still in its nascent stage. The majority of the embedded applications are divided between an 8-bit microcontroller implementation and a 32-bit processor-based real time operating system (RTOS) implementation. This text provides a starting point for the design of embedded system using FPGA and HDL. To give the text a common thread of thought from the application point of view, a design example of a hypothetical industrial robot controller is taken up. Different chapters of the text provide the necessary background on FPGA and HDL along with its use in designing an industrial robot controller.

CONTENTS:

Abbreviations........................................................................................................ xv
1 Introduction....................................................................................................... 1
 1.1  Embedded System Overview..................................................................... 1
1.2 Hypothetical Robot Control System .......................................................... 2
1.3 Digital Design Platforms ........................................................................... 4
 1.3.1 Microprocessor-based Design ........................................................ 5
 1.3.2 Single-chip Computer/Microcontroller-based Design.................... 7
  1.3.3  Application Specific Standard Products (ASSPs)........................... 8
  1.3.4  Design Using FPGA ..................................................................... 10
 1.4  Organization of the Book......................................................................... 12
Problems ........................................................................................................... 14
References ………………………………........................................................ 15
 Further Reading………………….. .................................................................. 16
2  Hardware Description Language: Verilog.................................................... 17
2.1 Software and HardwareDescription Languages...................................... 17
 2.2  Let’s Use Verilog as Our HDL!............................................................... 19
 2.3  Design Examples Using Verilog.............................................................. 19
 2.3.1 Gate Level Model......................................................................... 20
 2.3.2 Combinational CircuitsUsing Data Flow Modelling ................... 21
 2.3.3 Behavioural Logic ........................................................................ 24   2.3.4 Finite State Machine (FSM) ......................................................... 27
  2.3.5  Arithmetic Using HDL ................................................................. 35
2.4 Pipelining…… . ....................................................................................... 40
2.5 Module Instantiation and Port Mapping .................................................. 40
 2.6  Use of Pre-designed HDL Codes............................................................. 45
2.7 Simulating Digital Logic Using Verilog.................................................. 47
  2.7.1  EDA Tool Flow for Simulation .................................................... 47
  2.7.2  Creating a Test Bench for HDL-based Digital Logic ................... 49
  2.7.3  Post Place and Route Simulation.................................................. 49
  2.7.4  Simulation of Algorithm Using Pre-designed Codes.................... 51
xii Contents
Problems ........................................................................................................... 51
Further Reading………………….. .................................................................. 51
3 FPGA Devices.................................................................................................. 53
 3.1  FPGA and CPLD ..................................................................................... 53
3.2 Architecture of a FPGA ........................................................................... 54
 3.2.1 FPGA Interconnect Technology ................................................... 54
 3.2.2 Logic Cell..................................................................................... 56   3.2.3 FPGA Memory ............................................................................. 61   3.2.4 Clock Distribution and Scaling..................................................... 67
 3.2.5 I/O Standards ................................................................................ 70   3.2.6 Multipliers .................................................................................... 71
 3.3  Floor Plan and Routing ............................................................................ 72
 3.4  Timing Model for a FPGA....................................................................... 74
 3.5  FPGA Power Usage ................................................................................. 75
Problems ........................................................................................................... 79
Further Reading……………. ........................................................................... 80
4 FPGA-based Embedded Processor................................................................ 81
4.1 Hardware–Software Task Partitioning..................................................... 81
 4.2  FPGA Fabric Immersed Processors ......................................................... 82
 4.2.1 Soft Processors ............................................................................. 82   4.2.2 Hard Processors ............................................................................ 84    4.2.3  Tool Flow for Hardware–Software Co-design ............................. 84
4.3 Interfacing Memoryto the Processor....................................................... 85
4.4 Interfacing Processor with Peripherals .................................................... 86
 4.4.1 Types of On-chip Interfaces ......................................................... 88
 4.4.2 Wishbone Interface....................................................................... 89   4.4.3 Avalon Switch Matrix .................................................................. 90
 4.4.4 OPB Bus Interface........................................................................ 90  4.5 Design Re-use Using On-chip Bus Interface ........................................... 92
 4.6  Creating a Customized Microcontroller................................................... 94
 4.7  Robot Axis Position Control.................................................................... 98
Problems ......................................................................................................... 100
References…………………........................................................................... 101
Further Reading……………. ......................................................................... 101
5  FPGA-based Signal Interfacing and Conditioning.................................... 103
5.1 Serial Data Communication................................................................... 103
 5.2  Physical Layer for Serial Communication ............................................. 106
  5.2.1  RS-232-based Point-to-Point Communication ........................... 106
 5.2.2 RS-485-based Multi-point Communication................................ 106
5.3 Serial PeripheralInterface (SPI) ............................................................ 109
5.4 Signal Conditioning with FPGAs .......................................................... 111
Problems ......................................................................................................... 113
References……………………....................................................................... 114
Contents xiii
6  Motor Control Using FPGA......................................................................... 115
6.1 Introduction toMotor Drives ................................................................. 115
 6.2  Digital Block Diagram for Robot Axis Control..................................... 115
 6.2.1 Position Loop.............................................................................. 116
 6.2.2 Speed Loop................................................................................. 117   6.2.3 Power Module ............................................................................ 118   6.3  Case Studies for Motor Control ............................................................. 119
 6.3.1 Stepper Motor Controller............................................................ 119
 6.3.2 Permanent Magnet DC Motor .................................................... 122
  6.3.3  Brushless DC Motor ................................................................... 125
  6.3.4  Permanent Magnet Rotor (PMR) Synchronous Motor ............... 126
  6.3.5  Permanent Magnet Synchronous Motor (PMSM) ...................... 131
Problems ......................................................................................................... 135
Further Reading…………… .......................................................................... 136
7  Prototyping Using FPGA............................................................................. 139
 7.1  Prototyping Using FPGAs ..................................................................... 139
 7.2  Test Environment for the Robot Controller ........................................... 142
 7.3  FPGA Design Test Methodology........................................................... 143
  7.3.1  UART for Software Testing ....................................................... 143
  7.3.2  FPGA Hardware Testing Methodology...................................... 144
Problems ......................................................................................................... 151
References…………………........................................................................... 152
Index.................................................................................................................... 153

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