EBOOK - Designing Audio Power Amplifiers (Bob Cordell) | Cộng đồng Kỹ thuật cơ điện Việt Nam EBOOKBKMT

EBOOK - Thiết kế bộ khuếch đại công suất âm thanh (Bob Cordell) - 641 Trang.

This comprehensive book on audio power amplifier design will appeal to members of the professional audio engineering community as well as the hobbyist. Designing Audio Power Amplifiers begins with power amplifier design basics that a novice can understand and moves all the way through to in-depth design techniques for the very sophisticated audiophile and professional audio power amplifier designer. This is the single best source of knowledge for anyone who wants to design an audio power amplifier, whether for fun or profit. Develop and hone your audio design skills with in-depth coverage of these and other topics:

CONTENTS:

Part 1 Audio Power Amplifier Basics ..................................................... 1
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Organization of the Book ............................... 3
1.2 The Role of the Power Amplifier ......................... 4
1.3 Basic Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . 5
Rated Output Power ................................. 5
Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Additional Performance Specifications . . . . . . . . . . . . . . . . . . . 7
Damping Factor ..................................... 8
Dynamic Headroom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Slew Rate ........................................... 9
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Minimum Load Impedance ........................... 10
1.5 Output Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Basic Amplifier Topology ............................... 11
1.7 Summary ............................................. 14
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Power Amplifier Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 About Transistors ...................................... 15
Current Gain ........................................ 15
Base-Emitter Voltage ................................. 16
The Gummel Plot .................................... 17
Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Resistance ..................................... 19
Early Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Junction Capacitance ................................. 20
The Hybrid Pi Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
The Ideal Transistor .................................. 23
Safe Operating Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
JFETs and MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2 Circuit Building Blocks ................................. 25
Common-Emitter Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Bandwidth of the Common-Emitter Stage and Miller Effect . . 27
Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Emitter Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Cascode ............................................ 33
Current Mirror ...................................... 34
Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Vbe
Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.3 Amplifier Design Analysis .............................. 41
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
The VAS ............................................ 43
Open-Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Miller Feedback Compensation ........................ 45
The Output Stage .................................... 47
Output Stage Bias Current ............................ 49
Performance Limitations of the Simple Amplifier . . . . . . . . 50
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3 Power Amplifier Design Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.1 The Basic Power Amplifier .............................. 53
3.2 Adding Input Stage Degeneration . . . . . . . . . . . . . . . . . . . . . . . 55
3.3 Adding a Darlington VAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4 Input Stage Current Mirror Load . . . . . . . . . . . . . . . . . . . . . . . . 62
3.5 The Output Triple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.6 Cascoded VAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.7 Paralleling Output Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.8 Higher-Power Amplifiers ............................... 72
3.9 Crossover Distortion ................................... 73
3.10 Performance Summary ................................. 75
3.11 Completing an Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Input Network ...................................... 75
Feedback AC Decoupling Network . . . . . . . . . . . . . . . . . . . . 76
Output Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Power Supply Decoupling ............................ 77
3.12 Summary ............................................. 77
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4 Negative Feedback Compensation and Slew Rate ............... 79
4.1 How Negative Feedback Works . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2 Input-Referred Feedback Analysis . . . . . . . . . . . . . . . . . . . . . . . 80
4.3 Feedback Compensation and Stability .................... 81
Poles and Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Phase and Gain Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Gain and Phase Variation ............................. 84
4.4 Feedback Compensation Principles . . . . . . . . . . . . . . . . . . . . . . 84
Dominant Pole Compensation ......................... 84
Excess Phase ........................................ 84
Lag Compensation ................................... 85
Miller Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.5 Evaluating Loop Gain .................................. 87
Breaking the Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Exposing Open-Loop Gain ............................ 89
Simulation .......................................... 89
4.6 Evaluating Stability .................................... 89
Probing Internal Nodes in Simulation . . . . . . . . . . . . . . . . . . 90
Checking Gain Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Checking Phase Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Recommendations ................................... 91
4.7 Compensation Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.8 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Calculating the Required Miller Capacitance . . . . . . . . . . . . 93
Slew Rate ........................................... 94
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5 Amplifier Classes, Output Stages, and Efficiency ................ 97
5.1 Class A, AB, and B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.2 The Complementary Emitter Follower Output Stage . . . . . . . 98
Output Stage Voltage Gain ............................ 99
The Optimal Class AB Bias Condition . . . . . . . . . . . . . . . . . . 101
Output Stage Bias Current ............................ 101
gmDoubling ........................................ 102
The Small Class A Region of Many Amplifiers ........... 103
5.3 Output Stage Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Heat versus Sound Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Estimating Power Dissipation ......................... 104
Estimating the Input Power ........................... 104
An Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.4 Complementary Feedback Pair Output Stages ............. 105
The Quasi-Complementary Output Stage ............... 106
The CFP Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Biasing and Thermal Stability . . . . . . . . . . . . . . . . . . . . . . . . . 107
Optimum Class AB Bias Point and gmDoubling ......... 107
High-Frequency Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Turn-Off Issues in CFP Output Stages . . . . . . . . . . . . . . . . . . 107
Miller Effect in the CFP Output Stage . . . . . . . . . . . . . . . . . . 108
CFP Triples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
CFP Degeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.5 Stacked Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Cascode Output Stage ................................ 110
Soft Rail Regulation .................................. 110
5.6 Classes G and H ....................................... 110
Conflicting Terminology .............................. 110
Class G Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Class G Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Choice of Intermediate Rail Voltage .................... 113
Headroom Considerations ............................ 113
Rail Commutation Diode Speed . . . . . . . . . . . . . . . . . . . . . . . 114
The Transition to Cascode Operation ................... 114
Safe Operating Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.7 Class D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6 Summary of Amplifier Design Considerations .................. 117
6.1 Power and Loads ...................................... 117
Worst-Case Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Peak Output Current ................................. 117
Slew Rate ........................................... 118
6.2 Sizing the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Average Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . 118
Sizing the Power Transformer ......................... 118
Sizing the Reservoir Capacitors ........................ 119
6.3 Sizing the Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Number of Output Pairs .............................. 119
6.4 Sizing the Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
A Simple Guideline .................................. 120
6.5 Protecting the Amplifier and Loudspeaker ................ 121
Loudspeaker Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Safe Area Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.6 Power and Ground Distribution ......................... 121
When Ground Is Not Ground . . . . . . . . . . . . . . . . . . . . . . . . . 122
Ground Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Nonlinear Power Supply Currents ..................... 122
Current Flows Through the Shortest Path ............... 122
6.7 Other Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Output Stage Bias and Thermal Stability ................ 122
Output Node Catch Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Protection of Speaker Relay Contacts ................... 123
Physical Design and Layout ........................... 123
The Feedback Path ................................... 123
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Part 2 Advanced Power Amplifier Design Techniques .............................. 125
7 Input and VAS Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.1 Single-Ended IPS-VAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Improved Single-Ended IPS-VAS . . . . . . . . . . . . . . . . . . . . . . 128
Shortcomings of the Single-Ended IPS-VAS . . . . . . . . . . . . . 128
Opportunities for Further Improvement ................ 130
Input Stage Stress .................................... 130
7.2 JFET Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
JFET Transistors ..................................... 132
Behavior ............................ 133
JFET RFI Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Voltage Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
JFET Input Pairs and Matching ........................ 136
7.3 Complementary IPS and Push-Pull VAS .................. 136
Complementary IPS with Current Mirrors . . . . . . . . . . . . . . 137
Complementary IPS with JFETs . . . . . . . . . . . . . . . . . . . . . . . 140
Floating Complementary JFET-IPS ..................... 141
Complementary IPS with Unipolar JFETs . . . . . . . . . . . . . . . 142
7.4 Unipolar Input Stage and Push-Pull VAS . . . . . . . . . . . . . . . . . 142
Differential Pair VAS with Current Mirror . . . . . . . . . . . . . . 143
IPS with Differential Current Mirror Load . . . . . . . . . . . . . . 144
7.5 Input Common Mode Distortion . . . . . . . . . . . . . . . . . . . . . . . . 146
7.6 Early Effect ........................................... 147
7.7 Baker Clamps ......................................... 148
7.8 Amplifier Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Noise Power ........................................ 148
Noise Bandwidth .................................... 149
Noise Voltage Density ................................ 149
Relating Input Noise Density to Signal-to-Noise Ratio .... 149
A-Weighted Noise Specifications . . . . . . . . . . . . . . . . . . . . . . 149
VAS Noise .......................................... 150
Power Supply Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Resistor Noise ....................................... 151
Shot Noise .......................................... 151
BJT Input Noise Current .............................. 152
Noise of a Degenerated LTP ........................... 152
JFET Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Noise Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8 DC Servos .................................................. 155
8.1 Origins and Consequences of DC Offset . . . . . . . . . . . . . . . . . . 156
Input Bias Current ................................... 156
Conflicting Impedance Requirements . . . . . . . . . . . . . . . . . . 157
Bypassed Equalizing Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 158
DC-Coupled Feedback Network ....................... 158
Complementary Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . 159
DC Trim Pots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
JFET Input Stages .................................... 160
8.2 DC Servo Basics ....................................... 160
DC Servo Architectures ............................... 161
Setting the Low-Frequency Corner ..................... 161
Amount of Offset to Be Corrected ...................... 162
xii Contents
Servo Control Range ................................. 163
Servo Clipping ...................................... 163
Servo Headroom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
The JFET Advantage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
8.3 The Servo Is in the Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Servo Op Amp Distortion and Noise . . . . . . . . . . . . . . . . . . . 164
Adding a Second Pole ................................ 165
8.4 DC Offset Detection and Protection . . . . . . . . . . . . . . . . . . . . . . 167
8.5 DC Servo Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
8.6 Eliminating the Input Coupling Capacitor . . . . . . . . . . . . . . . . 169
8.7 DC Servo Design Issues and Nuances . . . . . . . . . . . . . . . . . . . . 169
Servo Start-Up Transients ............................. 169
Low-Frequency Testing of Amplifiers
Employing Servos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Simulation .......................................... 169
9 Advanced Forms of Feedback Compensation ................... 171
9.1 Understanding Stability Issues . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Dominant Pole Compensation ......................... 172
9.2 Miller Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Pole-Splitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Limitation on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Distortion Reduction as a Free Side Benefit .............. 175
VAS Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
The Feed-Forward Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Inserting a Zero to Cancel or Mitigate a Pole . . . . . . . . . . . . 176
Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Buffered Miller Feedback Pick-Off Point ................ 177
9.3 Two-Pole Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Conditional Stability ................................. 179
Frequency Response Peaking and Overshoot ............ 180
9.4 Miller Input Compensation ............................. 180
Combining the Best of Input and Miller
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Compensating the Compensation Loop ................. 181
9.5 Transitional Miller Compensation . . . . . . . . . . . . . . . . . . . . . . . 182
9.6 The Summing Node Pole ............................... 183
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
10 Output Stage Design and Crossover Distortion . . . . . . . . . . . . . . . . . 185
10.1 The Class AB Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Class B or Class AB? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
10.2 Static Crossover Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Crossover Distortion as a Function of Signal Level . . . . . . . 188
10.3 Optimum Bias and Bias Stability . . . . . . . . . . . . . . . . . . . . . . . . 188
Setting the Bias ...................................... 189
Bias Stability ........................................ 189
Dynamic Bias Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
The Bias Spreader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
10.4 Output Stage Driver Circuits ............................ 190
Darlington Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
The Triple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
The Diamond Driver ................................. 191
10.5 Output Transistor Matching Considerations ............... 193
Beta Matching ....................................... 193
Emitter and Base Resistance Matching .................. 194
Base Stopper Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
10.6 Dynamic Crossover Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Transistor Turn-Off Current Requirements . . . . . . . . . . . . . . 195
An Example BJT Power Transistor . . . . . . . . . . . . . . . . . . . . . 197
Turning Off the Transistor under Conditions of
Droop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
The Role of Collector-Base Capacitance ................. 198
The Speedup Capacitor ............................... 199
Current Slew Rate Requirements . . . . . . . . . . . . . . . . . . . . . . 200
10.7 The Output Emitter Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Paralleled Emitter Resistors ........................... 201
10.8 Output Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
The Zobel Network .................................. 202
Distributed Zobel Networks . . . . . . . . . . . . . . . . . . . . . . . . . . 203
The Series L-R Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
The Effect of the Coil on Sound Quality ................. 203
Variations on the Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
The Pi Output Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Eliminating the Output Coil . . . . . . . . . . . . . . . . . . . . . . . . . . 204
10.9 Output Stage Frequency Response and Stability . . . . . . . . . . . 205
Variation with Operating Point ........................ 205
Base Stopper Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Load Capacitance .................................... 206
Excess Phase ........................................ 207
Gain and Phase Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Stabilizing the Triple ................................. 207
10.10 Sizing the Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Safe Operating Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
10.11 Delivering High Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Driving Low-Impedance Loads ........................ 210
Loudspeaker Peak Current Requirements ............... 210
Beta Droop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Droop ............................................ 211
Safe Operating Area of the Driver ...................... 211
xiv Contents
10.12 Driving Paralleled Output Stages ........................ 212
Output Transistor Current Sharing ..................... 212
Output Transistor Capacitances . . . . . . . . . . . . . . . . . . . . . . . 212
10.13 Advanced Output Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
11 MOSFET Power Amplifiers ................................... 215
11.1 MOSFET Types and Characteristics . . . . . . . . . . . . . . . . . . . . . . 216
Lateral MOSFET Structure ............................ 217
Vertical MOSFET Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
11.2 MOSFET Advantages and Disadvantages ................. 218
Freedom from Second Breakdown and
Device Protection ................................... 218
Fragile Gate Oxide ................................... 220
The Body Diode ..................................... 220
Supply of High Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
The Role of Rds(on)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
High Speed ......................................... 223
Transconductance Frequency Response ................. 223
MOSFET Disadvantages and Caveats . . . . . . . . . . . . . . . . . . 223
MOSFETs versus Bipolar Transistors . . . . . . . . . . . . . . . . . . . 224
11.3 Lateral versus Vertical Power MOSFETs . . . . . . . . . . . . . . . . . . 224
11.4 Parasitic Oscillations ................................... 225
Gate Stopper Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Origin of Parasitic Oscillations . . . . . . . . . . . . . . . . . . . . . . . . 225
MOSFET Internal Inductances ......................... 226
MOSFET Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . 226
Gate Zobel Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Ferrite Beads ........................................ 227
Paralleled MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Spotting Parasitic Oscillations ......................... 227
11.5 Biasing Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Crossover Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Bias Spreaders for MOSFET Output Stages .............. 228
Dynamic Thermal Bias Stability . . . . . . . . . . . . . . . . . . . . . . . 229
11.6 Crossover Distortion ................................... 231
Transconductance Droop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Absence of gmDoubling .............................. 232
Use of Source Resistors ............................... 233
Wingspread Simulations .............................. 233
Memory Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
11.7 Driving Power MOSFETs ............................... 234
Driving the Gate Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . 235
Gate-Source Capacitance ............................. 235
Gate-Drain Capacitance .............................. 235
Contents xv
Required Drive Current versus Slew Rate ............... 236
Excess Phase at Signal Peaks . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Driving Multiple Output Pairs . . . . . . . . . . . . . . . . . . . . . . . . 236
Maximum Drive Considerations ....................... 237
Gate Protection ...................................... 237
Flying Catch Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Natural Current Limiting ............................. 238
Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Folded Drivers ...................................... 238
Boosted Driver Supplies .............................. 240
11.8 Paralleling and Matching MOSFETs ...................... 240
11.9 Simulating MOSFET Power Amplifiers ................... 241
High-Frequency Simulations .......................... 243
11.10 A MOSFET Power Amplifier Design . . . . . . . . . . . . . . . . . . . . . 243
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
12 Error Correction ............................................. 245
12.1 Feed-Forward Error Correction .......................... 245
Reduced Effectiveness at High Frequencies . . . . . . . . . . . . . 246
12.2 Hawksford Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
A Specialized Form of Negative Feedback . . . . . . . . . . . . . . 247
Frequency Compensation ............................. 248
Effect on Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . 248
12.3 Error Correction for MOSFET Output Stages .............. 248
Simplified Error-Correction Circuit . . . . . . . . . . . . . . . . . . . . 249
Error-Correction Circuit Operating Voltage . . . . . . . . . . . . . 250
Error-Correction Circuit Clipping ...................... 250
12.4 Stability and Compensation ............................. 250
Stability Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Frequency Compensation Approach . . . . . . . . . . . . . . . . . . . 251
Simulation of Effective Gain Crossover
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Effect on the Global Feedback Loop .................... 252
12.5 Performance and Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . 253
Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
High-Frequency Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Nonlinearity in the Error Amplifier .................... 254
Headroom and Clipping .............................. 255
Boosted Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Use with Low-Vgs
MOSFETs ........................... 255
Error Correction for BJT Output Stages . . . . . . . . . . . . . . . . . 256
12.6 Circuit Refinements and Nuances . . . . . . . . . . . . . . . . . . . . . . . . 257
Complementary Error Amplifier ....................... 257
CFP Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Cascoded Drivers .................................... 258
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
13 Other Sources of Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.1 Distortion Mechanisms ................................. 261
13.2 Early Effect Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
13.3 Junction Capacitance Distortion . . . . . . . . . . . . . . . . . . . . . . . . . 262
MOSFET Gate Capacitance Nonlinearity . . . . . . . . . . . . . . . . 262
13.4 Grounding Distortion .................................. 263
13.5 Power Rail Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Output Stage Power Supply Rejection .................. 264
13.6 Input Common Mode Distortion . . . . . . . . . . . . . . . . . . . . . . . . 264
Testing for Common Mode Distortion .................. 264
13.7 Resistor Distortion ..................................... 264
13.8 Capacitor Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
13.9 Inductor and Magnetic Distortions ....................... 267
Magnetic Core Distortion ............................. 267
Distortion from Proximity to Ferrous Materials .......... 268
Ferrite Beads ........................................ 268
13.10 Magnetic Induction Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Minimizing Magnetic Induction Distortion . . . . . . . . . . . . . . 268
13.11 Fuse, Relay, and Connector Distortion .................... 268
Fuse Distortion ...................................... 269
Relay Distortion ..................................... 269
Connector Distortion ................................. 272
13.12 Load-Induced Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
13.13 EMI-Induced Distortion ................................ 273
13.14 Thermally Induced Distortion (Memory Distortion) ........ 273
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Part 3 Real-World Design Considerations .............................................. 275
14 Output Stage Thermal Design and Stability .................... 277
14.1 Power Dissipation versus Power and Load . . . . . . . . . . . . . . . 277
14.2 Thermal Design Concepts and Thermal Models . . . . . . . . . . . 279
Temperature versus Log Time Plots . . . . . . . . . . . . . . . . . . . . 280
Thermal Attenuation ................................. 280
Lumped and Distributed Models . . . . . . . . . . . . . . . . . . . . . . 281
Transient Thermal Impedance ......................... 281
Thermal Simulation .................................. 282
Measuring Heat Sink Thermal Resistance ............... 284
14.3 Transistor Power Ratings ............................... 285
Transistor Insulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
14.4 Sizing the Heat Sink ................................... 286
Output Stage Power Dissipation ....................... 287
Required Heat Sink Thermal Resistance . . . . . . . . . . . . . . . . 287
Power Dissipation into Reactive Loads . . . . . . . . . . . . . . . . . 287
Transistor Junction Temperature ....................... 287
The Thermal Breaker ................................. 288
The Finger Test ...................................... 288
The Heat Sink Is Not Isothermal ....................... 288
Sizing the Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
14.5 The Bias Spreader and Temperature Compensation . . . . . . . . 290
The Vbe
Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Vbe
Multiplier Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Vbe
Multiplier Variations .............................. 293
Darlington Bias Spreaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
CFP Bias Spreaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Location of the Sensing Junction ....................... 295
Isothermal Bias Spreader and Driver Circuit . . . . . . . . . . . . 296
Thermal Attenuation Revisited ........................ 296
Setting the Bias and the Temperature Compensation . . . . . 297
Biasing Lateral Power MOSFETs ....................... 297
Biasing Vertical Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . 298
14.6 Thermal Bias Stability .................................. 299
Local Bias Stability ................................... 299
Base Stopper Resistors and Thermal Bias Stability ........ 302
Measuring Thermal Bias Stability ...................... 302
Bias Stability of MOSFETs versus BJTs .................. 302
14.7 Thermal Lag Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
14.8 ThermalTrak™ Power Transistors . . . . . . . . . . . . . . . . . . . . . . . . 304
Construction and Physical Characteristics . . . . . . . . . . . . . . 304
Bias Spreaders Employing ThermalTrak™
Transistors ......................................... 305
Tracking Diode Temperature Characteristics . . . . . . . . . . . . 307
Thermal Model ...................................... 307
Tracking Diode Response Time ........................ 309
Thermal Attenuation ................................. 310
Compensation of Predriver and Driver . . . . . . . . . . . . . . . . . 310
Bias as a Function of Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
THD as a Function of Bias Setting ...................... 312
ThermalTrak™ Transistors as Part of a Monitoring
and Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
15 Safe Area and Short Circuit Protection ......................... 315
15.1 Power Transistor Safe Operating Area .................... 315
Secondary Breakdown Mechanism ..................... 316
Temperature Derating of SOA ......................... 317
Transient SOA ....................................... 317
Long-Term Reliability and Destruct Point ............... 317
Managing Risk ...................................... 318
15.2 Output Stage Safe Operating Area . . . . . . . . . . . . . . . . . . . . . . . 318
Resistive Loads ...................................... 318
Reactive Loads ...................................... 318
xviii Contents
Impedance and Conductance as a Function of
Phase Angle ........................................ 320
Overlapped Elliptical Load Lines . . . . . . . . . . . . . . . . . . . . . . 322
15.3 Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Rail Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
A Simple Current Limiter ............................. 325
Natural Current Limiting ............................. 326
Shutdown Circuits ................................... 327
Speaker Relays ...................................... 328
Load-Sensing Circuits ................................ 328
15.4 Safe-Area-Limiting Circuits ............................. 329
Single-Slope V-ILimiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Multi-Slope V-I Limiters .............................. 331
Drawbacks of V-ILimiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Flyback Protection Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Avoiding the Use of V-ILimiters ....................... 333
15.5 Testing Safe-Area-Limiting Circuits ...................... 333
Simulation of Protection Circuits . . . . . . . . . . . . . . . . . . . . . . 334
15.6 Protection Circuits for MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . 334
15.7 Protecting the Driver Transistors . . . . . . . . . . . . . . . . . . . . . . . . 334
15.8 Loudspeaker Protection Circuits ......................... 335
Speaker Fuses ....................................... 335
The Speaker Relay and Its Control . . . . . . . . . . . . . . . . . . . . . 335
The TA7317 Loudspeaker Protection IC ................. 336
Protecting the Speaker Relay .......................... 338
Closing the Feedback Loop Around a Protection Device . . 339
Crowbar Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Avoiding Speaker Relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Protection Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
16 Power Supplies and Grounding ............................... 343
16.1 The Design of the Power Supply ......................... 343
Alternative Supply Arrangements . . . . . . . . . . . . . . . . . . . . . 343
Boosted Supply Rails ................................. 344
Power Supply Stiffness and Regulation ................. 345
Effective Power Supply Resistance ..................... 346
16.2 Sizing the Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
VA Rating Rules of Thumb ............................ 347
VA versus Weight .................................... 347
Toroid versus Conventional ........................... 347
Modifying Toroidal Transformers ...................... 348
16.3 Sizing the Rectifier ..................................... 348
16.4 Sizing the Reservoir Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Equivalent Series Resistance (ESR) and
Inductance (ESL) ................................... 349
Contents xix
Bypasses and Snubbers for Reservoir Capacitors ......... 350
Split Reservoir Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
16.5 Rectifier Speed ........................................ 351
Soft Recovery and Fast Recovery . . . . . . . . . . . . . . . . . . . . . . 352
Rectifier Noise and Snubbers .......................... 352
Measuring Rectifier Performance . . . . . . . . . . . . . . . . . . . . . . 352
16.6 Regulation and Active Smoothing of the Supply ........... 353
Regulation of Input and VAS Power Supplies . . . . . . . . . . . 354
16.7 SPICE Simulation of Power Supplies ..................... 354
16.8 Soft-Start Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Passive Soft-Start Circuits ............................. 355
Active Soft-Start Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
16.9 Grounding Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Noisy and Quiet Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
When Ground Is Not Ground . . . . . . . . . . . . . . . . . . . . . . . . . 357
Star Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Star-on-Star Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Ground Corruption .................................. 358
Dual-Mono Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
16.10 Radiated Magnetic Fields ............................... 359
Antenna Loop Area .................................. 359
Circuit Path Crossing Angle ........................... 359
16.11 Safety Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Safety Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Breaking Safety Ground Loops . . . . . . . . . . . . . . . . . . . . . . . . 359
16.12 DC on the Mains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
16.13 Switching Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
17 Clipping Control and Civilized Amplifier Behavior . . . . . . . . . . . . . 363
17.1 The Incidence of Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Clipping Experiments ................................ 364
17.2 Clipping and Sticking .................................. 364
17.3 Negative Feedback and Clipping . . . . . . . . . . . . . . . . . . . . . . . . 364
17.4 Baker Clamps ......................................... 365
Flying Baker Clamps and Flying
Catch Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Feedback Baker Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
17.5 Soft Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
The Klever Klipper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
17.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Active Current Limiting .............................. 370
Natural Current Limiting ............................. 370
17.7 Parasitic Oscillation Bursts .............................. 370
17.8 Optional Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
xx Contents
18 Interfacing the Real World . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
18.1 The Amplifier-Loudspeaker Interface . . . . . . . . . . . . . . . . . . . . 373
The Loudspeaker Is Not a Resistive Load . . . . . . . . . . . . . . . 373
Transmission Line Effects of Speaker Cables ............. 375
18.2 EMI Ingress: Antennas Everywhere ...................... 376
RFI and EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
EMI Ingress from the Amplifier Input . . . . . . . . . . . . . . . . . . 376
Implications for Input Stage Design .................... 378
EMI Ingress from the Loudspeaker Cable ............... 378
Implications for Output Network Design . . . . . . . . . . . . . . . 379
Implications for Feedback Network Design . . . . . . . . . . . . . 379
EMI Ingress from the Mains ........................... 379
EMI Distortion Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . 379
18.3 Input Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Achieving a Linear Phase Response .................... 380
18.4 Input Ground Loops ................................... 380
Ground Break Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Balanced Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Interconnect Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
18.5 Mains Filtering ........................................ 381
Line Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Ferrites and Inductors ................................ 381
18.6 EMI Egress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
18.7 EMI Susceptibility Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Cell Phones and Electric Drills . . . . . . . . . . . . . . . . . . . . . . . . 381
EMI Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Part 4 Simulation and Measurement .................................................... 383
19 SPICE Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
19.1 LTspice ............................................... 385
Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
The Toolbars ........................................ 386
Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Help ............................................... 387
The LTspice Users’ Group ............................. 387
19.2 Schematic Capture ..................................... 387
Placing Components ................................. 388
Picking and Placing Transistors ........................ 389
Other Components and Subcircuit Libraries ............. 389
Parameterized Elements .............................. 389
Completing the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
19.3 DC, AC, and Transient Simulation . . . . . . . . . . . . . . . . . . . . . . . 390
The DC Operating Point .............................. 390
The SPICE Error Log ................................. 391
Convergence ........................................ 391
AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Transient Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
19.4 Distortion Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
FFT Spectral Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Optimizing FFT Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
19.5 Noise Analysis ........................................ 396
Noise of Individual Contributors . . . . . . . . . . . . . . . . . . . . . . 397
Weighted Noise Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . 397
19.6 Controlled Voltage and Current Sources .................. 397
19.7 Swept and Stepped Simulations . . . . . . . . . . . . . . . . . . . . . . . . . 398
DC Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
DC Transfer ......................................... 398
Stepped Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Example: A Wingspread Simulation .................... 399
19.8 Plotting Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Gummel Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
19.9 Subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Creating a Subcircuit ................................. 403
The Symbol Editor ................................... 404
Modifying an Existing Symbol . . . . . . . . . . . . . . . . . . . . . . . . 405
Summary for Creating the LPF1 Symbol ................ 405
Using the Subcircuit in a Schematic . . . . . . . . . . . . . . . . . . . . 405
Installing Subcircuit Models in a Library ................ 405
19.10 SPICE Models ......................................... 406
Bipolar Junction Transistors ........................... 406
Junction Field Effect Transistors . . . . . . . . . . . . . . . . . . . . . . . 406
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Include Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
19.11 Simulating a Power Amplifier ........................... 408
DC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
1-kHz Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
20-kHz Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Square-Wave Response ............................... 411
1-kHz Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . 411
20-kHz THD ........................................ 412
CCIF Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . 413
Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Damping Factor and Output Impedance ................ 415
Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Inferring Loop Gain .................................. 415
xxii Contents
Measuring Loop Gain ................................ 416
Output Stage Power Dissipation ....................... 416
Output Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Safe Operating Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
20 SPICE Models and Libraries .................................. 419
20.1 Verifying SPICE Models ................................ 420
The Hybrid Pi Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
20.2 Tweaking SPICE Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
A Typical SPICE Model File ........................... 421
Base-Emitter Voltage ................................. 422
Current Gain ........................................ 423
Speed .............................................. 423
Base-Emitter Capacitance ............................. 424
Base-Collector Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
20.3 Creating a SPICE Model ................................ 424
Gathering Data Sheet Information . . . . . . . . . . . . . . . . . . . . . 425
Measuring Device Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Saturation Current and Nominal Vbe
Early Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Nominal Beta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Beta Droop at High and Low Current . . . . . . . . . . . . . . . . . . 429
Establish RB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Establish RB at High Base Current . . . . . . . . . . . . . . . . . . . . . 434
Establish Nominal Transit Time and fT
Droop at Low Current . . . . . . . . . . . . . . . . . . . . . 437
Determine Base-Collector Capacitance . . . . . . . . . . . . . . . . . 439
Check the Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
BJT Model Example .................................. 439
20.4 JFET Models .......................................... 440
DC Behavior of JFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
The JFET SPICE Model ............................... 441
Creating and Tweaking the JFET Model . . . . . . . . . . . . . . . . 441
20.5 Vertical Power MOSFET Models ......................... 442
Establishing the DC Parameters . . . . . . . . . . . . . . . . . . . . . . . 442
Gate-Source Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Gate-Drain Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Cgd
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
The Subcircuit Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Subthreshold Conduction ............................. 446
Applicability ........................................ 447
Power Amplifier Design Concerns ..................... 447
20.6 LTspice™ VDMOS Models .............................. 447
Establishing the Model Parameters . . . . . . . . . . . . . . . . . . . . 448
Applicability ........................................ 449
20.7 The EKV Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Subthreshold MOSFET Measurements . . . . . . . . . . . . . . . . . 452
Model Creation Procedure ............................ 453
Applicability ........................................ 454
20.8 Hybrid VDMOS-EKV Model ............................ 454
20.9 Lateral Power MOSFETs ................................ 455
20.10 Installing Models ...................................... 456
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
21 Audio Instrumentation ....................................... 459
21.1 Basic Audio Test Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Audio Oscillator ..................................... 459
AC Voltmeter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Oscilloscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
21.2 Dummy Loads ........................................ 460
Choose Load Resistors Wisely ......................... 460
Inductive versus Noninductive ........................ 460
Power Dissipation and Cooling ........................ 461
Connecting to the Dummy Load ....................... 461
21.3 Simulated Loudspeaker Loads . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Protection Circuit Testing ............................. 462
21.4 THD Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Interpreting Results .................................. 463
Spectral Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Obtaining a THD Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
21.5 PC-Based Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Sound Card Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Sound Cards ........................................ 465
PC-Based Oscilloscopes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
21.6 Purpose-Built Test Gear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Sound Card Interface Boxes ........................... 465
The Distortion Magnifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Balanced Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
IM Test Signal Combiner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Synchronous Tone Burst Generator . . . . . . . . . . . . . . . . . . . . 468
Signal-to-Noise Measurement Preamp with
A Weighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Powering Purpose-Built Test Equipment ................ 469
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
22 Distortion and Its Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
22.1 Nonlinearity and Its Consequences . . . . . . . . . . . . . . . . . . . . . . 471
The Order of a Nonlinearity ........................... 472
22.2 Total Harmonic Distortion .............................. 472
Interpretation of THD ................................ 472
Advantages of THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Limitations of THD .................................. 474
22.3 SMPTE IM ............................................ 474
22.4 CCIF IM .............................................. 475
22.5 TIM and SID .......................................... 476
Slew Rate Limiting and Input Stage Stress . . . . . . . . . . . . . . 476
The DIM Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
THD-20 Will Always Accompany TIM . . . . . . . . . . . . . . . . . . 477
22.6 PIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Differential Gain and Phase ........................... 478
Measuring PIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Negative Feedback and PIM . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Input Stage Stress .................................... 480
PIM in Amplifiers Without Negative
Feedback .......................................... 480
22.7 IIM .................................................. 480
Loudspeaker emf and Peak Current
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
High-Current Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . 482
Measuring IIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Open-Loop Output Impedance ........................ 483
22.8 Multitone Intermodulation Distortion .................... 484
22.9 Highly Sensitive Distortion Measurement . . . . . . . . . . . . . . . . 484
22.10 Input-Referred Distortion Analysis . . . . . . . . . . . . . . . . . . . . . . 485
Input Referral Breaks the Feedback Loop . . . . . . . . . . . . . . . 485
Input Referral Demonstrates Why High Forward-Path
Gain Reduces Distortion ............................. 485
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
23 Other Amplifier Tests ........................................ 489
23.1 Measuring Damping Factor ............................. 489
23.2 Sniffing Parasitic Oscillations . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
23.3 EMI Ingress Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
23.4 Burst Power and Peak Current . . . . . . . . . . . . . . . . . . . . . . . . . . 492
23.5 PSRR Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
23.6 Low-Frequency Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Beat Frequency Tests ................................. 493
23.7 Back-Feeding Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Back-Fed Beat Frequency Test . . . . . . . . . . . . . . . . . . . . . . . . . 494
THD-20 in the Presence of Low-Frequency
Back-Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Current-Induced Distortion Tests . . . . . . . . . . . . . . . . . . . . . . 495
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Part 5 Topics in Amplifier Design .......................................................... 497
24 The Negative Feedback Controversy ........................... 499
24.1 How Negative Feedback Got Its Bad Rap ................. 499
Amplifier Limitations of the 1970s . . . . . . . . . . . . . . . . . . . . . 499
Guilt by Association . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
TIM, PIM, and IIM ................................... 500
24.2 Negative Feedback and Open-Loop Bandwidth . . . . . . . . . . . 500
The Input Stage Error Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 500
24.3 Spectral Growth Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Baxandall’s Findings ................................. 502
Real-World Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Degeneration and SGD ............................... 503
SGD and Crossover Distortion . . . . . . . . . . . . . . . . . . . . . . . . 504
24.4 Global versus Local Feedback ........................... 505
24.5 Timeliness of Correction ................................ 505
24.6 EMI from the Speaker Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
24.7 Stability and Burst Oscillations .......................... 505
24.8 Clipping Behavior ..................................... 506
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
25 Amplifiers Without Negative Feedback . . . . . . . . . . . . . . . . . . . . . . . . 509
25.1 Design Trade-Offs and Challenges ....................... 509
Input Stage Dynamic Range and Distortion . . . . . . . . . . . . . 510
JFET Input Buffers ................................... 512
Cascoding the Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Gain Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Controlling VAS Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
VAS Noise .......................................... 514
Amplifiers with Local Negative Feedback ............... 515
Output Stage Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
MOSFET Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Damping Factor ..................................... 517
Power Supply Rejection and Power Supply Design . . . . . . 518
DC Offset ........................................... 518
Balanced Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
25.2 Additional Design Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 519
A Complementary IPS-VAS ........................... 519
The Cascomp Input Stage ............................. 520
25.3 An Example Design with No Feedback ................... 522
25.4 A Feedback Amplifier with Wide Open-Loop
Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
Achieving Wide Open-Loop Bandwidth ................ 524
A 200-W MOSFET Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
xxvi Contents
26 Balanced and Bridged Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
26.1 Balanced Input Amplifiers .............................. 527
Gain and Input Impedance Considerations .............. 527
Single and Triple Op-Amp Solutions . . . . . . . . . . . . . . . . . . . 528
Configuring the Power Amplifier as a Differential
Amplifier .......................................... 529
The Differential Complementary
Feedback Quad (DCFQ) ............................. 530
26.2 Bridged Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Sound Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Power Supply Advantages ............................ 532
26.3 Balanced Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
True Balanced Amplifiers ............................. 533
Differential-Mode Feedback ........................... 533
Differential-Mode DC Servo . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Common-Mode DC Servo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
27 Integrated Circuit Power Amplifiers and Drivers ................ 537
27.1 IC Power Amplifiers ................................... 537
27.2 The Gain Clones ....................................... 538
A Basic Gain Clone Design ............................ 538
A Gain Clone Using the Inverting Mode ................ 538
Avoiding Electrolytic Capacitors While Controlling Offset ... 539
27.3 The Super Gain Clone .................................. 539
Input Circuits ....................................... 539
Power Amplifier ..................................... 541
Output Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
DC Servo ........................................... 541
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
27.4 Integrated Circuit Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
The LME49810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
The LME49830 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
27.5 An Integrated Circuit Bias Controller ..................... 544
Compensation of the Amplifier ........................ 547
Compensation of the LT1166 . . . . . . . . . . . . . . . . . . . . . . . . . . 548
A Non-Switching Amplifier ........................... 548
A MOSFET Power Amplifier Using the LT1166
and LME49830 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
27.6 Summary ............................................. 550
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Part 6 Class D Amplifiers ...................................................................... 551
28 Class D Audio Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
28.1 How Class D Amplifiers Work . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Analog Class D and Digital Class D .................... 555
Synchronous and Asynchronous Class D . . . . . . . . . . . . . . . 555
28.2 Buck Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
Synchronous Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . 557
Gate Drive Requirements and Power Dissipation . . . . . . . . 558
Gate Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
MOSFET Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Conduction Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Switching Loss ...................................... 561
Reverse Recovery Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
28.3 Class D Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Single-Ended and H-Bridge Output Stages .............. 562
N-Channel Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Gate Drive Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Adaptive Dead Time Control .......................... 564
28.4 Summary ............................................. 564
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
29 Class D Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
29.1 The Output Filter and EMI .............................. 565
The Zobel Network .................................. 567
Differing Loudspeaker Impedance ..................... 567
Linear Phase Approximation .......................... 567
Reducing Output Filter Size ........................... 567
Input Filter and Aliasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Other EMI Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Output Filter Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
29.2 Sources of Distortion ................................... 569
Triangle Reference Linearity and Bandwidth . . . . . . . . . . . . 569
Pulse Width Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Dead Time .......................................... 569
PWM Crossover Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
The PWM Central Region ............................. 572
Extending the PWM Central Region .................... 573
Asymmetrical Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . 573
Body Diode Conduction Time ......................... 573
Sliver Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
29.3 Bus Pumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
29.4 Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Loop Gain Modulation ............................... 576
Power Supply Feedback to the Triangle Generator . . . . . . . 576
29.5 Power Supplies for Class D Amplifiers . . . . . . . . . . . . . . . . . . . 576
Linear Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Switching Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
29.6 Negative Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
Closing the Loop Before the Output Filter ............... 578
Closing the Loop Around the Output Filter . . . . . . . . . . . . . 579
29.7 Damping Factor and Load Invariance . . . . . . . . . . . . . . . . . . . . 580
29.8 Summary ............................................. 581
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
30 Alternative Class D Modulators ............................... 583
30.1 Self-Oscillating Loops .................................. 583
Self-Oscillation with Pre-filter Feedback . . . . . . . . . . . . . . . . 584
Self-Oscillation with the Output Filter .................. 585
Self-Oscillation Using a One-Shot ...................... 585
Synchronized Self-Oscillating Loops . . . . . . . . . . . . . . . . . . . 586
30.2 Sigma-Delta Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
Oversampling ....................................... 588
High-Speed Class D Sigma-Delta Amplifiers . . . . . . . . . . . . 589
High Sigma-Delta Modulator Clock Frequencies ......... 590
Adaptive Transition Density Limiting . . . . . . . . . . . . . . . . . . 590
Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Second-Order Sigma-Delta Modulators ................. 591
Higher-Order Sigma-Delta Modulators ................. 592
EMI of Sigma-Delta Class D Amplifiers ................. 592
The Output Filter .................................... 592
Post-Filter Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
30.3 Digital Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Digital PWM Modulators ............................. 593
Digital Sigma-Delta Modulators ....................... 593
Feedback and PSRR .................................. 593
References .................................................. 594
31 Class D Measurement, Performance, and Efficiency . . . . . . . . . . . . . 595
31.1 Hybrid Class D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
31.2 Measuring Class D Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
The AES17 Filter ..................................... 597
Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
SMPTE IM .......................................... 598
CCIF Tests .......................................... 598
Aliasing ............................................ 598
PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Conductive Emissions ................................ 599
31.3 Achievable Performance ................................ 599
Efficiency ........................................... 599
Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

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